An Efficient VLSI Architecture Design for Sisoand LDPC Based Advanced Turbo Decoder

نویسندگان

  • P.Senthilkumar
  • M. Rekha
چکیده

To achieve the high data rate requirements of emerging wireless communication technologies, the iterative turbo decoding architecture have been proposed and it requires the use of parallel architectures to implement high throughput Turbo decoder. Turbo decoder consists of SISO decoder, LDPC Decoder, interleaver and deinterleaver. Contention-free Unified parallel Confection and balance scheduling scheme suitable for parallel decoding of codes. In this paper, we propose highly parallel Turbo decoders with scalable a posteriori algorithm for every type of parallelism with various block sizes and high throughput rates. The performance of this architecture can further be improved by modifying the same with an LDPC (Low Density Parity Check) decoder and matched filter, so that the accuracy of the decoder data can be improved, the time required for the execution can also be

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes

The most powerful channel coding schemes, namely those based on turbo codes and low-density parity-check (LDPC) Gallager codes, have in common the principle of iterative decoding. However, the relative coding structures and decoding algorithms are substantially different. This paper presents a 2048-bit, rate-1/2 soft decision decoder for a new class of codes known as Turbo Gallager Codes. These...

متن کامل

High-throughput LDPC decoders

A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design—namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder ...

متن کامل

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for lowdensity parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of applicat...

متن کامل

SLATE: A Combined Architecture for LDPC and Turbo Decoding

LDPC and turbo codes are channel codes commonly used for wireless communication. Decoding algorithms are computationally demanding, and so efficient implementations are often inflexible, targeting only the codes specified by a given standard. When support for multiple standards is needed, multiple decoders are generally used. We study the algorithms for decoding each standard and find that some...

متن کامل

A Flexible LDPC/Turbo Decoder Architecture

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2015