An Efficient VLSI Architecture Design for Sisoand LDPC Based Advanced Turbo Decoder
نویسندگان
چکیده
To achieve the high data rate requirements of emerging wireless communication technologies, the iterative turbo decoding architecture have been proposed and it requires the use of parallel architectures to implement high throughput Turbo decoder. Turbo decoder consists of SISO decoder, LDPC Decoder, interleaver and deinterleaver. Contention-free Unified parallel Confection and balance scheduling scheme suitable for parallel decoding of codes. In this paper, we propose highly parallel Turbo decoders with scalable a posteriori algorithm for every type of parallelism with various block sizes and high throughput rates. The performance of this architecture can further be improved by modifying the same with an LDPC (Low Density Parity Check) decoder and matched filter, so that the accuracy of the decoder data can be improved, the time required for the execution can also be
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